DO-254 FPGA Level In-Target Testing
DO-254/CTS™ is a certifiable at-speed FPGA level in-hardware verification environment dedicated to address the stringent guidelines of DO-254 Section 6 Verification Process. It provides a feasible solution such that FPGA level requirements are easily preserved and verified from RTL simulation to hardware...
Prototyping in a FLASH!
Aldec® and Microsemi have joined together, offering a new, innovative, reprogrammable prototyping solution for Microsemi RTAX-S/SL, RTAX-DSP and RTSX-SU space-fight system designs. Unlike the traditional OTP (One Time Programmable) anti-fuse space-qualified FPGAs, the Aldec prototype adaptor uses...
Large FPGA and ASIC Verification
Riviera-PRO is a multi-platform, high-performance, mixed-language RTL and gate-level simulator for ASIC and FPGA designs. Riviera-PRO includes advanced debugging tools and support of advanced verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level...
FPGA Design “Made easy”
Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synthesis and implementation...
Design Rule Checking ALINT™ design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents them from spreading into the downstream stages of design flow. The tool features highly customizable and intuitive framework that...
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